1. Field of the Invention
This invention relates to a method of designing and testing electronic assemblies; and more specifically a method of designing electronic assemblies, having both logic and memory, and a method of testing such embedded memory and logic, using a combined logic and memory tester.
2. Description of the Prior Art
Current methods for testing electronic equipment include various methods which individually test each printed circuit board used in the assembled equipment.
Board level automatic test equipment (ATE) intended for general purpose application utilizes either of (or a combination of) two approaches: in-circuit test (ICT) or functional board test (FBT). ICT is an attempt to test individual components of an assembly one-by-one, by providing stimulus directly to the device singled out for test. Instead of using a card-edge connector, an in-circuit test is usually administered by mounting the printed circuit board in a multiple-pin (bed-of-nails) fixture. The fixture pins, which are usually brought into contact with test points (nodes) on the board by vacuum actuation, are configured so as to contact every node on the circuit board. A different test fixture is fabricated for each circuit board type being tested so that the pins line up with the nodes.
Providing test stimulus for digital devices requires overdriving the outputs of devices of the assembly that control the target device (i.e., component to be tested) during functional operation of the unit. While the possibility of damaging these other devices, by forcing them to an opposite state, has been empirically shown to be of little current practical significance, this problem will continue to exist, and may even become insurmountable at some point in the evolution of integrated circuits. In many cases, the overdrive capability of the tester is inadequate to deal with particular devices, requiring that the forcing be accomplished at a previous level of logic (i.e., earlier in the circuit paths). Such fixes interfere with diagnostic accuracy, typically being beyond the scope of the tester software (i.e., the program that controls the execution of the ATE tester sequence) to fully, or even largely, integrate. The advent of Advanced Schottky devices, such as the Texas Instruments Incorporated "AS Series", produce an even greater demand on tester hardware and software.
Driver current cannot be increased at the expense of slew rate (i.e., rate of change of voltage), however, since device operation is often dependent on some minimum risetime. More current switching in a shorter time produces increased noise to further complicate tester design goals. The inability to prevent spikes when overdriven circuits attempt to change states, as an indirect result of stimulus to the target device, often requires that other devices be preconditioned to prevent such feedback. Since the algorithms to accomplish this guarding (i.e., precondition to prevent feedback) must deal with device functionality, the tester software must increase in capability at a rate coupled with the change of device complexity. As fewer small scale integrated (SSI) circuits or medium scale integrated (MSI) circuits devices are used, not only will tester software have to be exceedingly complex to identify these feedback loops, but it will often be unable to find a point at which to inject the guarding stimulus.
The drivers to provide the needed stimulus over a variety of integrated circuit logic families are necessarily expensive. Individual driver cost is a major issue where the need for more than a thousand drivers per tester is not uncommon.
ICT stimulus problems notwithstanding, there is no guarantee that the inability of the target device to produce a correct level is caused by an internal fault. Wired-or's, marginal shorts, or loading by other devices are possibilities which require further analysis merely to be discounted. While the problems of developing techniques to deal with these situations do not seem beyond solution, the cure is already far behind the need. Furthermore, the use of devices having connections accessible only on the side of the printed circuit board contacting the bed-of-nails, will likely tax a solution applicable to devices packaged in dual-in-line-packages (DIP's).
In-circuit testing, then, must deal with a variety of problems not fully appreciable when the possible ability to test a single device at a time seems the central issue. The ICT problems may be summarized as follows:
(1) Overdriving requirements. PA1 (2) Possible device damage. PA1 (3) Necessity to guard. PA1 (4) Bed-of-nail contact. PA1 (5) Reliance on etch. PA1 (6) Intra-node diagnosis. PA1 (7) Driver cost. PA1 (1) Repeatability not easily attainable. PA1 (2) Long development time. PA1 (3) Over-reliance on design for testability. PA1 (4) Diagnostic quality indeterminate. PA1 (5) Sensitivity to design changes. PA1 (6) Mutually exclusive features.
The functional board test approach is an attempt to provide stimulus and check responses at the external connections of an assembly, usually at the board's edge connections, in much the same fashion as the unit would function in a system environment. To predict the state of external connections, for error detection; and internal points, for fault diagnosis, requires extensive tester software. While the alternative of eliminating this software and learning the responses has been used in some FBT efforts, the disadvantages of doing so outweigh the cost advantage immediately gained in most cases.
If it were true that an assembly, correctly designed from a utilization standpoint, would always respond in the same manner to given stimulus, the only problems to be reckoned with using this approach would involve timing repeatability from one test to another or from one tester to another. However, it is generally incumbent upon the hardware designer only that all such assemblies respond to user stimulus in the same user-visible manner. This requires that a complex board to be tested with an FBT tester be designed for repeatability rather than merely for functionality.
The degree of repeatability necessary depends upon the resolution of the tester. Currently, tester vendors tout nanosecond capabilities, but these figures apply only to hardware control which is not fully integrated into the tester software. This degree of precision, however, would have to be supported by something even more complex than the present stored-pattern concept. Even without such resolution, differences found between a sample board and simulator generated patterns may require manual masking of the response to be checked for at a particular point. Such masking obviously degrades the diagnostic process, adding to the number of cases where a problem may be detected but escapes diagnosis, while often involving repeated lengthy attempts at isolation.
The quality of an FBT program to efficiently resolve faults correctly--as opposed to getting lost or requiring scores of probes on even a small board--is difficult to determine. While it would seem likely that the probing algorithm could be applied as an option in faults simulation, such a feature has not been noted in FBT primary vendor literature, if indeed it exists at all. However, considering that it may take several months to generate FBT patterns with sufficient comprehensiveness of detection, and that solving the diagnostic problem could greatly extend the time, it is not necessarily in the best interest of the tester vendor to provide even more hurdles for the tester programmer. Meanwhile, however, higher levels of integration make mass part changes less acceptable when the test system fails.
Long tester program development times cannot be said to be reduced by automatic test vector generators, as they are characteristically ineffective on complex boards. A simple logic change may produce nearly catastrophic results on a test program even during this long manual development stage. The reliance upon product stability means that FBT cannot be depended upon as a predictable fault elimination mechanism throughout a typical product life cycle.
Currently, users are satisfied with comprehensiveness figures measured in terms of "stuck-at" faults (i.e., a fault that causes a point to remain at logic 0 or 1 throughout the test sequence). Exact definitions vary from vendor to vendor. Dynamic faults simulation is desirable, of course, but the tester software problems are probably insurmountable. As it is, one major vendor estimated the time for faults simulation of a 7000 gate equivalent device exercised by 4000 vectors to consume sixteen hours of CPU time. While those involved with memory testing stress pattern sensitivity checks, and while logic becomes more and more dense, the stuck-at evaluations become less and less meaningful.
While a number of hardware additions have been made to offset tester software inadequacies, especially in dealing with analog circuits, it is often found that features cannot be used together. For example, fault diagnosis involving current tracing to determine whether the error is attributable to a defect in the source driver or one of its loads may not be available for use when the tester is applying patterns at fast rates.
Major unresolved problem areas in the FBT approach are:
Until recently, when electronic systems, such as computers which contained memories comprised of a plurality of integrated circuit chips were built, the memory was usually partitioned into one electronic assembly such as a printed circuit board and the other combinatorial logic within the system was usually packaged in other electronic assemblies separate from the memory. During the manufacturing of these partitioned systems, the electronic assembly containing in the memory could be tested by using a memory tester which in most cases would connect to an edge connector on the memory's printed circuit board and exercise the memory and evaluate the test the results. The other electronic assemblies, which contain the combinatorial logic, would be tested by a separate in-circuit tester which would usually make contact with the electronic assembly by using a bed-of-nails fixture. Alternatively, the electronic assembly could be tested using a functional board tester which would be connected to the edge connectors of the electronic assembly. Until now this approach has worked fairly well allowing the memory to be thoroughly tested by the memory tester and the other logic to be thoroughly tested by a logic tester, each tester being able to be specialized such that the tests that are most important for the elements it is testing can be conducted with an acceptable degree of precision and thoroughness.
More recently, with the advent of higher density circuits, more complex products, and larger printed circuit boards, the trend in the industry is to have an increasing number of electronic assemblies (printed circuit boards) which contain memory arrays embedded within the boards which also contain combinatorial logic. Many electronic assemblies, such as found in CRT terminals used in computer systems, now contain a fairly substantial amount of MOS or bipolar read-only memory (ROM) and random access memory (RAM) packed in integrated circuit chips mounted on the printed circuit boards. These ROMS and RAMS should be tested to the same extent memories used in main memory boards are tested. Typically, memory boards require testing on a memory test system which permits parametric test to be conducted such that parameters may be modified to insure that a large percentage of "soft" errors can be detected. These "soft" errors do not occur consistently, but are errors which occur when the memory is operating under marginal conditions. This embedding of the memory arrays within the electronic assemblies has presented a problem as to how to test the board during manufacture or repair because of the difficulty in setting up the necessary inputs to the memory array and in measuring the outputs. Attempting to perform memory tests using standard in-circuit test philosophies have generally resulted in the abandonment of a parametric test for the memory and to be satisfied with simply a gross test of the memory. Unfortunately, experience with: memory array integrated circuits, the natures of the circuits themselves, and the opinions of experts in the field of memory arrays indicate that the abandoning of the parametric tests with respect to memory arrays is not wise and can be expected to lead to system failures in the field as the memory arrays which are marginal fail.
Currently the testing of logic elements for pattern sensitivity and AC parameters is not considered as vital as it is for memory arrays in the vast majority of cases. In general, the testing of the logic elements in an electronic assembly for their static functionality by use of ICT techniques is considered largely adequate with the number of problems that will go undetected from not having more fully tested the logic elements being considered not a major consequence. However, in the case of integrated circuit memory arrays, it is generally felt that the memories must be tested dynamically at speed in order to adequately test the memory. Therefore, one of the main distinctions between a memory test system, which may be considered to be a specialized FBT system, and an in-circuit logic tester is the fact that, in general, logic testers do not function at the same speeds required of a memory test system. Although, if possible, the testing of logic elements at dynamic speeds is desirable, it is felt to be very critical in the case of memory arrays because they are susceptible to pattern sensitivity problems that may occur only when operated under dynamic conditions.
Other distinctions that exist between memory test systems and logic test systems are that memory test systems are relatively straightforward to change when switching from the testing of one device to another device. These changes being generally in the area of pattern selection so that a pattern is applied to the memory device that will detect problems associated with those for which the particular memory device may be susceptible. Changes are also in the area of the number of address, and data input, and data output bits that are associated with a particular memory array. Logic testers, on the other hand, have test programs which are generally more complex than those associated with memory arrays because the logic elements are not repeated as they are in memory arrays and therefore most logic test programs are more customized programs. A further distinction is that most memory testers attach to the electronic assembly under test (i.e., the memory) through use of edge connectors (the number of connections normally being in the hundreds), whereas most in-circuit logic testers use a bed-of-nails fixture to contact a very large number (into the thousands) of points on the electronic assembly.
An article entitled, "In-Circuit Testing Comes of Age" by Douglas W. Raymond, which compares in-circuit testing (ICT) with functional board testing (FBT) can be found in the August 1981 issue of Computer Design on pages 117-124, and is incorporated herein by reference.
Therefore, what is needed is an effective and efficient way to test integrated circuit arrays which are embedded within larger electronic assemblies.